Espressif Systems /ESP32-C2 /RTC_CNTL /CLK_CONF

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Interpret as CLK_CONF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EFUSE_CLK_FORCE_GATING)EFUSE_CLK_FORCE_GATING 0 (EFUSE_CLK_FORCE_NOGATING)EFUSE_CLK_FORCE_NOGATING 0 (CK8M_DIV_SEL_VLD)CK8M_DIV_SEL_VLD 0CK8M_DIV 0 (ENB_CK8M)ENB_CK8M 0 (ENB_CK8M_DIV)ENB_CK8M_DIV 0 (DIG_XTAL32K_EN)DIG_XTAL32K_EN 0 (DIG_CLK8M_D256_EN)DIG_CLK8M_D256_EN 0 (DIG_CLK8M_EN)DIG_CLK8M_EN 0CK8M_DIV_SEL 0 (XTAL_FORCE_NOGATING)XTAL_FORCE_NOGATING 0 (CK8M_FORCE_NOGATING)CK8M_FORCE_NOGATING 0CK8M_DFREQ0 (CK8M_FORCE_PD)CK8M_FORCE_PD 0 (CK8M_FORCE_PU)CK8M_FORCE_PU 0 (XTAL_GLOBAL_FORCE_GATING)XTAL_GLOBAL_FORCE_GATING 0 (XTAL_GLOBAL_FORCE_NOGATING)XTAL_GLOBAL_FORCE_NOGATING 0 (FAST_CLK_RTC_SEL)FAST_CLK_RTC_SEL 0ANA_CLK_RTC_SEL

Description

register description

Fields

EFUSE_CLK_FORCE_GATING

Need add desc

EFUSE_CLK_FORCE_NOGATING

Need add desc

CK8M_DIV_SEL_VLD

used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel

CK8M_DIV

CK8M_D256_OUT divider. 00: div128

ENB_CK8M

disable CK8M and CK8M_D256_OUT

ENB_CK8M_DIV

1: CK8M_D256_OUT is actually CK8M

DIG_XTAL32K_EN

enable CK_XTAL_32K for digital core (no relationship with RTC core)

DIG_CLK8M_D256_EN

enable CK8M_D256_OUT for digital core (no relationship with RTC core)

DIG_CLK8M_EN

enable CK8M for digital core (no relationship with RTC core)

CK8M_DIV_SEL

divider = reg_ck8m_div_sel + 1

XTAL_FORCE_NOGATING

XTAL force no gating during sleep

CK8M_FORCE_NOGATING

CK8M force no gating during sleep

CK8M_DFREQ

CK8M_DFREQ

CK8M_FORCE_PD

CK8M force power down

CK8M_FORCE_PU

CK8M force power up

XTAL_GLOBAL_FORCE_GATING

Need add desc

XTAL_GLOBAL_FORCE_NOGATING

Need add desc

FAST_CLK_RTC_SEL

fast_clk_rtc sel. 0: XTAL div 4

ANA_CLK_RTC_SEL

Need add desc

Links

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